EDGESEL=FALLING, HYS=NOHYSTERESIS, COMPSA=DIRECT, COMP_VP_SEL=VLADOUT, COMP_VM_SEL=VLADDOUT
Comparator control register
| RESERVED | Reserved. Write as 0. |
| EDGESEL | This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below): 00 = Falling edges 01 = Rising edges 1x = Both edges 0 (FALLING): Falling edges 1 (RISING): Rising edges 2 (DUALEDGE): Both edges 3 (DUALEDGE): Both edges |
| RESERVED | Reserved. Write as 0. |
| COMPSA | Comarator output control 0 (DIRECT): Uses the comparator output directly. 1 (SYNCH): Synchronizes the comparator output to the bus clock for output to other modules. |
| RESERVED | Reserved. Write as 0. |
| COMP_VP_SEL | Selects positive voltage input 0 (VLADOUT): voltage ladder output 1 (ACMPI1): ACMPI1 2 (ACMPI2): ACMPI2 3 (ACMPI3): ACMPI3 4 (ACMPI4): ACMPI4 5 (ACMPI5): ACMPI5 6 (INTVOLTAGEREF): internal reference voltage 7 (TEMPSENSOR): temperature sensor |
| COMP_VM_SEL | Selects negative voltage input 0 (VLADDOUT): voltage ladder output 1 (ACMPI1): ACMPI1 2 (ACMPI2): ACMPI2 3 (ACMPI3): ACMPI3 4 (ACMPI4): ACMPI4 5 (ACMPI5): ACMPI5 6 (INTVOLTAGEREF): internal reference voltage |
| RESERVED | Reserved. Write as 0. |
| EDGECLR | Interrupt clear bit. Writing a 1 to this bit clears the COMPEDGE bit (bit 23 below) and thus negates the interrupt request. |
| COMPSTAT | Comparator status. This bit reflects the state of the comparator output. |
| RESERVED | Reserved. Write as 0. |
| COMPEDGE | Comparator edge-detect status. |
| RESERVED | Reserved. Write as 0. |
| HYS | Controls the hysteresis of the comparator. When the comparator is outputting a certain state, this is the difference between the selected signals, in the opposite direction from the state being output, that will switch the output. 0 (NOHYSTERESIS): None (the output will switch as the voltages cross) 1 (HYS5MV): 5 mV 2 (HSY10MV): 10 mV 3 (HSY20MV): 20 mV |
| RESERVED | Reserved |